AN49150 - Schematic and Layout Review Checklist for HX2LP | 赛普拉斯半导体
AN49150 - Schematic and Layout Review Checklist for HX2LP
AN49150 discusses the schematic and layout review checklist for the EZ-USB HX2LP™ family.
The Cypress CY7C65620 and CY7C65630 USB 2.0 hubs are high performance, low cost solutions for USB. The CY7C656xx USB 2.0 hubs integrate 1.5 kΩ upstream pull-up resistors for host notification. All downstream 15 kΩ pull-down resistors and series termination resistors are also integrated by the hubs on all upstream and downstream D+ and D- pins. This results in system cost optimization by providing built in support for the USB 2.0 specification.