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AN49150 - Schematic and Layout Review Checklist for HX2LP | 赛普拉斯半导体

AN49150 - Schematic and Layout Review Checklist for HX2LP

最近更新: 
2020 年 5 月 28 日
版本: 
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This is an Obsolete Application Note
The document AN49150 - Schematic and Layout Review Checklist for HX2LP has been marked as obsolete. The obsolete version of this application note is still available with the below description but may not be complete or valid any longer. If you have any questions or require support in regards to the below application note content, please click here and create a technical support case.

AN49150 discusses the schematic and layout review checklist for the EZ-USB HX2LP™ family.

简介

The Cypress CY7C65620 and CY7C65630 USB 2.0 hubs are high performance, low cost solutions for USB. The CY7C656xx USB 2.0 hubs integrate 1.5 kΩ upstream pull-up resistors for host notification. All downstream 15 kΩ pull-down resistors and series termination resistors are also integrated by the hubs on all upstream and downstream D+ and D- pins. This results in system cost optimization by providing built in support for the USB 2.0 specification.