AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide | 赛普拉斯半导体
AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide
Cypress Quad Data Rate™ (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 GBps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.
(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
For the full version of this message, please download the PDF version.
相关文件
文件标题 | 语言 | Size | 最近更新 |
---|---|---|---|
![]() |
英语 | 1.18 MB | 2015 年 08 月 26 日 |
![]() |
中文 | 1.3 MB | 2017 年 08 月 01 日 |
![]() |
日语 | 1.26 MB | 2015 年 08 月 26 日 |
需要帮助?提出问题并在赛普拉斯开发者社区论坛上寻找答案。
低/间断性带宽用户提示:如果您的连接在下载期间中断,Firefox 和 Chrome 浏览器可支持断点续传。
相关资源
AN42468 - On-Die Termination for QDR(R) II+/DDR II+ SRAMs | 2021 年 03 月 02 日 |
AN6017 - Differences in Implementation of 65 nm QDR™ II/DDR II and QDR II+/DDR II+ Memory Interfaces | 2015 年 11 月 23 日 |
AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details | 2020 年 05 月 14 日 |
AN84060 - QDR®-IV Design Guide | 2021 年 03 月 02 日 |