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AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide | 赛普拉斯半导体

AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide

最近更新: 
2020 年 5 月 14 日
版本: 
*I

Cypress Quad Data Rate™ (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 GBps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

Clock Controller Diagram

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)

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