You are here

AN46982 - PLL Considerations in QDR® - II/II+/DDR-II/II+ SRAMs | 赛普拉斯半导体

AN46982 - PLL Considerations in QDR® - II/II+/DDR-II/II+ SRAMs

最近更新: 
2020 年 5 月 28 日
版本: 
*G

AN46982 provides an overview of the operation of QDR-II/II+/DDR-II/II+ SRAMs in PLL disabled mode.

简介

QDR SRAM family of devices has a phase-locked loop (PLL) within the device to synchronize the output data to the input clocks thereby enabling the device to operate at higher frequencies.

QDR-II/II+/DDR-II/II+ devices can be operated with PLL enabled or PLL disabled. This application note provides an overview of the operation of the device when the PLL is disabled.

PLL Off Diagram