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AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM | 赛普拉斯半导体

AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM

最近更新: 
2021 年 3 月 02 日
版本: 
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Cypress’s serial peripheral interface (SPI) nvSRAM is a high-performance nonvolatile serial memory that offers zero cycle delay write operation and infinite SRAM write endurance. The SPI nvSRAM is a slave SPI device and requires an SPI master controller to access nvSRAM in a system. This application note provides a few key design considerations and firmware tips to guide the users designing with SPI nvSRAM. An associated project for PSoC 1 and a library component for PSoC 3 and PSoC 4 are also provided as an example project, which demonstrates SPI nvSRAM access by a standard SPI master controller.

SOC connection to SPI nvSRAM Diagram

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翻译文档仅作参考之用。我们建议您在参与设计开发时参考文档的英语版本。