AN66806 - Getting Started with EZ-USB® FX2LP™ GPIF | 赛普拉斯半导体
AN66806 - Getting Started with EZ-USB® FX2LP™ GPIF
This document introduces the GPIF unit and its graphical design tool called GPIF Designer by creating a simple design that divides the GPIF clock by 2, 4, and 7. Only three lines of C code are required to configure and manage this interface. The application note also includes an example demonstrating how to incorporate a USB connection into a GPIF design.
The 480 Mbps signaling rate of USB 2.0 requires the controller chip to move the high-speed data ON and OFF. The EZ-USB® FX2LP GPIF provides an independent hardware unit that the CPU sets up to move data directly to and from USB endpoint FIFOs to an external interface. The external interface can be a RAM, FIFO, or a second processor. Therefore, the CPU does not need to move data. When configured, the CPU only monitors flags and interrupts as the data flows over the GPIF hardware channel.
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