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AN74875 - Designing with Serial I2C nvSRAM | 赛普拉斯半导体

AN74875 - Designing with Serial I2C nvSRAM

最近更新: 
2018 年 1 月 29 日
版本: 
*E

A typical I2C single master-multi slave configuration is shown in the following diagram.

Serial I2C nvSRAM Diagram (AN74875)

This application note provides a few example circuits, design guidelines, and PSoC®3 based sample code snippets to help users understand and design with Cypress I2C nvSRAM.

An "I2C nvRAM" component library is also created using Cypress PSoC®3 device as a reference design project and attached to this Application Note. The PSoC®3 component library configures Cypress PSoC®3 device as a standard I2C master controller and also provides the list of APIs which can directly be called in an application firmware to access the I2C nvSRAM functions.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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翻译文档仅作参考之用。我们建议您在参与设计开发时参考文档的英语版本。