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AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details | 赛普拉斯半导体

AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details

最近更新: 
2020 年 5 月 14 日
版本: 
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简介

Cypress’s Radiation Hardened 72Mbit QDR®II+ is a source synchronous pipelined Static RAM equipped with the 1.8-V QDRII+ architecture with RadStop® technology. The QDRII+ architecture has separate data inputs and data outputs along with a common multiplexed address port. To maximize data throughput, both read and write ports are equipped with DDR interfaces which transfer data on both rising and falling edges of the clock signal. The result is that two/four bus widths of data are transferred during each clock period for Burst 2/Burst 4 configurations.