You are here

AN89371 - Power Saving With Cypress’s 65-nm Asynchronous PowerSnooze™ SRAM | 赛普拉斯半导体

AN89371 - Power Saving With Cypress’s 65-nm Asynchronous PowerSnooze™ SRAM

最近更新: 
2015 年 8 月 26 日
版本: 
*A

This application note explains the PowerSnoozeTM feature of Cypress’ 65-nm Asynchronous Fast SRAM devices (CY7S10xxG family). PowerSnooze allows the SRAM to enter into a low-power mode during long chip disable periods. A user-controlled pin (DS) allows seamless transition between high-speed mode and low-power mode. This application note also describes the critical timing parameters for the mode transitions as well as a sample SRAM interface configuration to use the PowerSnooze feature in application systems.

简介

With the advent of mobile technology and portable battery-backed devices, power consumption has become one of the key factors in system design. System designers face the dilemma of selecting between faster operating speeds and lower power consumption for the microcontrollers/ASICs, peripherals, and memory devices in their systems.

翻译文档仅作参考之用。我们建议您在参与设计开发时参考文档的英语版本。