Pulse Width Modulator (TCPWM_PWM_PDL) | 赛普拉斯半导体
Pulse Width Modulator (TCPWM_PWM_PDL)
The TCPWM_PWM_PDL Component is a graphical configuration entity built on top of the cy_tcpwm driver available in the PDL. It allows schematic-based connections and hardware configuration as defined by the Component Configure dialog.
The TCPWM_PWM_PDL Component is a wrapper around the TCPWM hardware that allows you to configure the TCPWM hardware for PWM Functionality. It allows for the creation of arbitrary digital waveforms. You can control the duty cycle and period of the TCPWM_PWM_PDL output signal. The TCPWM_PWM_PDL also provides a complementary output, with the possibility to insert dead time between the two outputs.
The TCPWM_PWM_PDL Component has several alignment options: Left, Right, Center, and Asymmetric. In all modes the period and compare value can be swapped to create an arbitrary waveform. It also has a pseudo random output mode.