Software Watchdog (PDL_SWWDG) | 赛普拉斯半导体
Software Watchdog (PDL_SWWDG)
The Software Watchdog is a 32-bit down counter that generates an interrupt, and optional reset, when the timer expires. The counter can be fed by a normally-functioning application to reset the counter and avoid the interrupt/reset. This enables the forced reset of a runaway application (one that fails to feed the watchdog).
The window mode forces the feed to occur after a configurable percentage of the counter period has expired. If the application attempts to feed the watchdog before the window opens, the interrupt fires immediately. This prevents poor watchdog design by preventing the constant feeding of the timer from the application.
The watchdog is clocked from a divided APB clock (PCLK) which enables the safe use of standby mode in your application. The counter automatically stops in the low power state and re-starts when the device wakes up.
SWWDG Component Parameter Editor