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Timer / Counter (TCPWM_Counter_PDL) | 赛普拉斯半导体

Timer / Counter (TCPWM_Counter_PDL)

最近更新: 
2018 年 3 月 26 日
版本: 
1.0
特性 符号图
  • 16- or 32-bit Timer/Counter
  • Programmable Period Register
  • Programmable Compare Register
    • Compare value can be swapped with a buffered compare value on comparison event
  • Input Capture with buffer register
  • Count Up, Count Down, or Count Up and Down Counting Modes
  • 连续或单触发模式
  • Interrupt and Output on Overflow, Underflow, Capture, or Compare
  • Start, Reload, Stop, Capture, and Count Inputs
  • Peripheral Driver Library (PDL) Component (PDL Application Programming Interface (API) only)
 

TCPWM Counter Image

 

概述

The TCPWM_Counter_PDL Component is a graphical configuration entity built on top of the cy_tcpwm driver available in the PDL. It allows schematic-based connections and hardware configuration as defined by the Component Configure dialog.

The TCPWM_Counter_PDL Component allows rapid configuration of the TCPWM hardware for Timer/Counter functionality. This Component provides a method to measure time intervals or count external events.