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Watch Counter (PDL_WC) | 赛普拉斯半导体

Watch Counter (PDL_WC)

最近更新: 
2018 年 2 月 27 日
版本: 
1.0
特性
  • 6-bit down counter
  • Prescaler generates a wide range of WC input clock frequencies
  • Supports low-power wakeup
符号图
Watch_Counter_Symbol Diagram

概述

The Watch Counter is a 6-bit down counter that optionally generates an interrupt on underflow. The period of the counter is controlled with the reload value and the clock from the prescaler, which offers four choices (WCCK0 to WCCK3) to the Watch Counter. The prescaler is set up in firmware with an API function to select the clock source and divider for each of the WCCKn clocks.

WC Component Parameter Editor

WC Component Parameter Editor