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CY14B512Q1, CY14B512Q2, CY14B512Q3: 512-Kbit (64 K × 8) Serial (SPI) nvSRAM | Cypress Semiconductor

CY14B512Q1, CY14B512Q2, CY14B512Q3: 512-Kbit (64 K × 8) Serial (SPI) nvSRAM

最近更新: 
2015 年 8 月 31 日
版本: 
*J

特性

  • 512-Kbit nonvolatile static random access memory (nvSRAM)
    • Internally organized as 64 K × 8
    • 在断电时自动启动 (AutoStore) 或者由用户使用 HSB 引脚(硬件 STORE)或 SPI 指令(软件 STORE)启动数据存储至量子井非易失性组件
    • 在通电时启动(通电 RECALL)或者由 SPI 指令(软件 RECALL)启动数据恢复至 SRAM
    • Automatic STORE on power-down with a small capacitor (except for CY14B512Q1)
  • 高可靠性
    • 无限的读、写和数据恢复循环
    • 1 百万次存储至量子井的循环
    • 数据保留时间:20 年
  • High speed serial peripheral interface (SPI)
    • 40 MHz clock rate
    • Supports SPI mode 0 (0,0) and mode 3 (1,1)
  • Write protection
    • Hardware protection using Write Protect (WP) pin
    • Software protection using Write Disable instruction
    • Software block protection for 1/4,1/2, or entire array
  • 低功耗
    • Single 3 V +20%, –10% operation
    • Average active current of 10 mA at 40 MHz operation
  • Industry standard configurations
    • 工业温度
    • CY14B512Q1 has identical pin configuration to industry standard 8-pin NV memory
    • 8-pin dual flat no-lead (DFN) package and 16-pin small outline integrated circuit (SOIC) package
    • Restriction of hazardous substances (RoHS) compliant

功能概述

The Cypress CY14B512Q1/CY14B512Q2/CY14B512Q3 combines a 512-Kbit nvSRAM with a nonvolatile element in each memory cell with serial SPI interface. 该存储器采用“64 K 字,每字 64 位”的组织方式。嵌入式非易失性组件通过采用量子井技术,打造出世界上最可靠的非易失性存储器。SRAM 能够实现无限次读写循环,而量子井单元则能够提供高度可靠的非易失性数据存储空间。Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14B512Q1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through SPI instruction.