You are here

CY29352: 2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer | 赛普拉斯半导体

CY29352: 2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer

最近更新: 
2020 年 6 月 08 日
版本: 
*F

2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer

特性

  • Output frequency range: 16.67 MHz to 200 MHz
  • Input frequency range: 16.67 MHz to 200 MHz
  • 工作电压:2.5V 或 3.3V
  • Split 2.5V and 3.3V outputs
  • ±2% maximum output duty cycle variation
  • 11 clock outputs: drive up to 22 clock lines
  • LVCMOS reference clock input
  • 125 ps maximum output-output skew
  • PLL bypass mode
  • 如需更多信息,请参阅 PDF 文档
     

Description

The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distribution applications.

The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in three banks of five, four, and two outputs.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.