CY2DL1504: 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input | 赛普拉斯半导体
CY2DL1504: 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input
1:4 Differential LVDS Fanout Buffer with Selectable Clock Input
Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs
Translates any single-ended input signal to 3.3 V LVDS levels with resistor bias on INx# input
30-ps maximum output-to-output skew
480-ps maximum propagation delay
0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
Up to 1.5-GHz operation
Output enable and synchronous clock enable functions
20-pin thin shrunk small outline package (TSSOP)
2.5-V or 3.3-V operating voltage
Commercial and industrial operating temperature range
The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between two separate differential (LVPECL, LVDS, HCSL, or CML) input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The output enable function allows the outputs to be asynchronously driven to a high-impedance state. The device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 GHz.
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