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CY7B9945V RoboClock®: High-Speed Multi-Phase PLL Clock Buffer Datasheet | 赛普拉斯半导体

CY7B9945V RoboClock®: High-Speed Multi-Phase PLL Clock Buffer Datasheet

最近更新: 
2019 年 4 月 30 日
版本: 
*P

High Speed Multi-phase PLL Clock Buffer

特性

  • 500 ps max Total Timing Budget (TTB™) window
  • 24 MHz –200 MHz input and Output Operation
  • Low Output-output skew <200 ps
  • 10 + 1 LVTTL Outputs driving 50Ω terminated lines
  • Dedicated feedback output
  • Phase adjustments in 625ps/1300 ps steps up to + 10.4 ns
  • 3.3V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable Reference Inputs
  • Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
  • Individual Output Bank Disable
  • 如需更多信息,请参阅 PDF 文档



功能描述

The CY7B9945V high speed multi-phase PLL clock buffer offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer and communication systems.