CY7C1268KV18, CY7C1270KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | 赛普拉斯半导体
CY7C1268KV18, CY7C1270KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
- 36 Mbit density (2 M × 18, 1 M × 36)
- 550 MHz 时钟实现高带宽
- 2 字突发降低地址总线频率
- 双数据速率 (DDR) 接口（数据传输速率 1100 MHz），工作频率 550 MHz
- 可提供 2.5 时钟周期延迟
- 两个输入时钟（K 和 K）用于精确 DDR 定时
- SRAM 仅使用上升沿
- 回波时钟（CQ 和 CQ）简化高速系统中的数据采集
- 如需更多信息，请参阅 PDF 文档
The CY7C1268KV18, and CY7C1270KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. DDR II+ 包含一个带有先进同步外围电路的 SRAM 内核。用于读和写的地址被锁止在输入 (K) 时钟的备选上升沿。Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C1268KV18), or 36-bit words (CY7C1270KV18) that burst sequentially into or out of the device..
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