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CY7C1302DV25: 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture | 赛普拉斯半导体

CY7C1302DV25: 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

最近更新: 
2017 年 11 月 30 日
版本: 
*J

9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

特性

  • 分立的独立读和写数据端口
    • 支持并发事务处理
  • 167-MHz clock for high bandwidth
    • 2.5 ns Clock-to-Valid access time
  • 所有访问均为 2 字突发
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
    • SRAM 仅使用上升沿
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C1302DV25 is a 2.5 V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. 读端口有专用的数据输出来支持读操作,写端口则有专用的数据输入来支持写操作。Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock.

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