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CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, CY7C1314JV18: 18-Mbit QDR® II SRAM 2-Word Burst Architecture | 赛普拉斯半导体

CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, CY7C1314JV18: 18-Mbit QDR® II SRAM 2-Word Burst Architecture

最近更新: 
2020 年 5 月 28 日
版本: 
*D

This product datasheet is no longer supported by Cypress. Please contact your local sales representative for more information.

18-Mbit QDR® II SRAM 2-Word Burst Architecture

特性

  • 分立的独立读和写数据端口
    • 支持并发事务处理
  • 250 MHz 时钟实现高带宽
  • 所有访问均为 2 字突发
  • 读和写端口上均为双数据速率 (DDR) 接口

    (数据传输速率 500 MHz),工作频率 250 MHz
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
    • SRAM 仅使用上升沿
  • 两个输入时钟用于输出数据(C 和 C),以将时钟偏移和飞行时间的不匹配降至最低
  • 回波时钟(CQ 和 CQ)简化高速系统中的数据采集
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, and CY7C1314JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: 即用于访问内存阵列的读端口和写端口。读端口具有数据输出来支持读操作,写端口则具有数据输入来支持写操作。

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.