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CY7C1312KV18, CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture | 赛普拉斯半导体

CY7C1312KV18, CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture

2017 年 11 月 30 日

18-Mbit QDR® II SRAM Two-Word Burst Architecture


  • 分立的独立读和写数据端口
    • 支持并发事务处理
  • 333 MHz 时钟实现高带宽
  • Two-word burst on all accesses
  • Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
    • SRAM 仅使用上升沿
  • 两个输入时钟用于输出数据(C 和 C),以将时钟偏移和飞行时间的不匹配降至最低
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • 单个复用地址输入总线,能够为读端口和写端口锁存地址输入


The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II 架构包含两个分立的端口:即用于访问内存阵列的读端口和写端口。读端口有专用的数据输出来支持读操作,写端口则有专用的数据输入来支持写操作。QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

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