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CY7C1351G: 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture | 赛普拉斯半导体

CY7C1351G: 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture

2020 年 6 月 09 日

4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture


  • Can support up to 133-MHz bus operations with zero wait states
    • Data is transferred on every clock
  • Pin compatible and functionally equivalent to ZBT™ devices
  • Internally self-timed output buffer control to eliminate the need to use OE
  • Registered inputs for flow-through operation
  • Byte write capability
  • 128 K × 36 common I/O architecture
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • 如需更多信息,请参阅 PDF 文档


The CY7C1351G is a 3.3 V, 128 K × 36 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

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Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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