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CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture | 赛普拉斯半导体

CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture

2016 年 11 月 21 日

4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture


  • Pin compatible and functionally equivalent to ZBT™ devices
  • Internally self-timed output buffer control to eliminate the need to use OE
  • Byte write capability
  • 256 K × 18 common I/O architecture
  • 3.3 V core power supply (VDD)
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 4.0 ns (for 133-MHz device)
  • Clock enable (CEN) pin to suspend operation
  • 如需更多信息,请参阅 PDF 文档


The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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