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CY7C1354C, CY7C1356C: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL Architecture | 赛普拉斯半导体

CY7C1354C, CY7C1356C: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL Architecture

最近更新: 
2018 年 4 月 09 日
版本: 
*T

9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture

特性

  • Pin-compatible and functionally equivalent to ZBT
  • Supports 250 MHz bus operations with zero wait states
    • Available speed grades are 250, 200, and 166 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte write capability
  • Single 3.3 V power supply (VDD)
  • 3.3 V or 2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C1354C/CY7C1356C are 3.3V, 256 K × 36/512 K × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™ logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C/CY7C1356C are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature greatly improves the throughput of data in systems that require frequent write/read transitions. The CY7C1354C/CY7C1356C are pin compatible and functionally equivalent to ZBT devices.