CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture | 赛普拉斯半导体
CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture
9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture
- Pin-compatible and functionally equivalent to ZBT
- Supports 200 MHz bus operations with zero wait states
- Available speed grade is 200 MHz
- Internally self-timed output buffer control to eliminate the need to use asynchronous OE
- Fully registered (inputs and outputs) for pipelined operation
- Byte write capability
- Single 3.3 V power supply (VDD)
- 3.3 V or 2.5 V I/O power supply (VDDQ)
- Fast clock-to-output times
- 3.2 ns (for 200 MHz device)
- 如需更多信息，请参阅 PDF 文档
The CY7C1354D are 3.3 V, 256 K × 36 synchronous pipelined burst SRAM with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
For the full version of this message, please download the PDF version.