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CY7C1366C, CY7C1367C: 9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM | 赛普拉斯半导体

CY7C1366C, CY7C1367C: 9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM

最近更新: 
2020 年 6 月 09 日
版本: 
*O

9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM

特性

  • Supports bus operation up to 166 MHz
  • Available speed grade is 166 MHz
  • Registered inputs and outputs for pipelined operation
    • Optimal for performance (double-cycle deselect)
      • Depth expansion without wait state
    • 3.3 V – 5% and 10% core power supply (VDD)
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 3.5 ns (for 166 MHz device)
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C1366C/CY7C1367C SRAM integrates 256 K × 36 and 512 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3 [1]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

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