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CY7C1371DV33: 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture | 赛普拉斯半导体

CY7C1371DV33: 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture

最近更新: 
2016 年 3 月 11 日
版本: 
*D

18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture

特性

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
  • Supports up to 133-MHz bus operations with zero wait states
  • Pin-compatible and functionally equivalent to ZBT™ devices
  • Internally self-timed output buffer control to eliminate the need to use OE
  • Registered inputs for flow through operation
  • Byte write capability
  • 3.3 V/2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • 如需更多信息,请参阅 PDF 文档
     

功能描述

The CY7C1371DV33 is a 3.3 V, 512 K × 36 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371DV33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

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