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CY7C1381D, CY7C1383D, CY7C1383F: 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM | 赛普拉斯半导体

CY7C1381D, CY7C1383D, CY7C1383F: 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM

2017 年 6 月 19 日

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM


  • Supports 133 MHz bus operations
  • 512K × 36 and 1M × 18 common I/O
  • 3.3V core power supply (VDD)
  • 2.5V or 3.3V I/O supply (VDDQ)
  • Fast clock-to-output time
    • 6.5 ns (133 MHz version)
  • Provides high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • 如需更多信息,请参阅 PDF 文档


The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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