CY7C1385D, 18-MBIT (512 K X 32) FLOW-THROUGH SRAM | 赛普拉斯半导体
CY7C1385D, 18-MBIT (512 K X 32) FLOW-THROUGH SRAM
18-Mbit (512 K × 32) Flow-Through SRAM
- Supports 133 MHz bus operations
- 512 K × 32 common I/O
- 3.3 V core power supply (VDD)
- 2.5 V or 3.3 V I/O supply (VDDQ)
- Fast clock-to-output time
- Provides high performance 2-1-1-1 access rate
- User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self-timed write
- Asynchronous output enable
- 如需更多信息，请参阅 PDF 文档
The CY7C1385D is a 3.3 V, 512 K × 32 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).
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