CY7C1392KV18, CY7C1393KV18: 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture | 赛普拉斯半导体
CY7C1392KV18, CY7C1393KV18: 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
- 18 Mbit density (2 M x 8, 1 M x 18)
- 333-MHz clock for high bandwidth
- 2 字突发降低地址总线频率
- 双数据速率 (DDR) 接口（数据传输速率 666 MHz），工作频率 333 MHz
- 如需更多信息，请参阅 PDF 文档
The CY7C1392KV18 and CY7C1393KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. DDR II SIO 包含两个分立的端口：即用于访问内存阵列的读端口和写端口。读端口具有数据输出来支持读操作，写端口则具有数据输入来支持写操作。The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. 用于读和写的地址被锁止在输入 (K) 时钟的备选上升沿。
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
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