CY7C1418KV18, CY7C1420KV18: 36-Mbit DDR II SRAM Two-Word Burst Architecture | 赛普拉斯半导体
CY7C1418KV18, CY7C1420KV18: 36-Mbit DDR II SRAM Two-Word Burst Architecture
36-Mbit DDR II SRAM Two-Word Burst Architecture
- 36-Mbit density (2 M × 18, 1 M × 36)
- 333 MHz 时钟实现高带宽
- 2 字突发降低地址总线频率
- 双数据速率 (DDR) 接口（数据传输速率 666 MHz），工作频率 333 MHz
- 两个输入时钟（K 和 K）用于精确 DDR 定时
- SRAM 仅使用上升沿
- 两个输入时钟用于输出数据（C 和 C），以将时钟偏移和飞行时间的不匹配降至最低
- 回波时钟（CQ 和 CQ）简化高速系统中的数据采集
- 如需更多信息，请参阅 PDF 文档
The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
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