CY7C1425KV18, CY7C1412KV18, CY7C1414KV18: 36-Mbit QDR® II SRAM Two-Word Burst Architecture | 赛普拉斯半导体
CY7C1425KV18, CY7C1412KV18, CY7C1414KV18: 36-Mbit QDR® II SRAM Two-Word Burst Architecture
36-Mbit QDR® II SRAM Two-Word Burst Architecture
- 333 MHz 时钟实现高带宽
- Two-word burst on all accesses
- 读和写端口均为双倍数据速率 (DDR) 接口（数据传输速率 666 MHz），工作频率 333 MHz
- 两个输入时钟（K 和 K）用于精确 DDR 定时
- SRAM 仅使用上升沿
- 两个输入时钟用于输出数据（C 和 C），以将时钟偏移和飞行时间的不匹配降至最低
- 回波时钟（CQ 和 CQ）简化高速系统中的数据采集
- 如需更多信息，请参阅 PDF 文档
The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II 架构包含两个分立的端口：即用于访问内存阵列的读端口和写端口。读端口有专用的数据输出来支持读操作，写端口则有专用的数据输入来支持写操作。QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.
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