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CY7C1480BV25: 72-Mbit (2 M × 36) Pipelined Sync SRAM | 赛普拉斯半导体

CY7C1480BV25: 72-Mbit (2 M × 36) Pipelined Sync SRAM

最近更新: 
2016 年 6 月 24 日
版本: 
*N

72-Mbit (2M x 36) Pipelined Sync SRAM

特性

  • Supports bus operation up to 250 MHz
  • Available speed grades are 250, 200, and 167 MHz
  • Registered inputs and outputs for pipelined operation
  • 2.5-V core power supply
  • 2.5-V I/O operation
  • Fast clock-to-output time
    • 3.0 ns (for 250 MHz device)
  • Provide high performance 3-1-1-1 access rate
  • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C1480BV25 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).