CY7C1481BV33: 72-Mbit (2 M × 36) Flow-Through SRAM | 赛普拉斯半导体
CY7C1481BV33: 72-Mbit (2 M × 36) Flow-Through SRAM
72-Mbit (2 M × 36) Flow-Through SRAM
- Supports 133 MHz bus operations
- 2 M × 36 common I/O
- 3.3 V core power supply (VDD)
- 2.5 V or 3.3 V I/O supply (VDDQ)
- Fast clock to output time
- 6.5 ns (133 MHz version)
- Provide high performance 2-1-1-1 access rate
- User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self timed write
- Asynchronous output enable
- CY7C1481BV33 available in JEDEC standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package.
- IEEE 1149.1 JTAG compatible boundary scan
- ZZ sleep mode option
- 如需更多信息，请参阅 PDF 文档
The CY7C1481BV33 is a 3.3 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).
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