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CY7C1484BV25: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM | 赛普拉斯半导体

CY7C1484BV25: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

最近更新: 
2016 年 1 月 08 日
版本: 
*D

72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

特性

  • Supports bus operation up to 250 MHz
  • Available speed grades are 250 MHz
  • Registered inputs and outputs for pipelined operation
  • Optimal for performance (double cycle deselect)
  • Depth expansion without wait state
  • 2.5 V core power supply (VDD)
  • 2.5 V I/O supply (VDDQ)
  • Fast clock to output times
    • 3.0 ns (for 250 MHz device)
  • Provide high performance 3-1-1-1 access rate
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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