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CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM Two-Word Burst Architecture | 赛普拉斯半导体

CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM Two-Word Burst Architecture

最近更新: 
2018 年 2 月 13 日
版本: 
*V

72-Mbit DDR II SRAM Two-Word Burst Architecture

特性

  • 72 Mbit 密度 (4M x 18, 2M x 36)
  • 333 MHz 时钟实现高带宽
  • 2 字突发降低地址总线频率
  • 双数据速率 (DDR) 接口(数据传输速率 666 MHz),工作频率 333 MHz
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
    • SRAM 仅使用上升沿
  • 两个输入时钟用于输出数据(C 和 C),以将时钟偏移和飞行时间的不匹配降至最低
  • 回波时钟(CQ 和 CQ)简化高速系统中的数据采集
  • 同步内部自定时写入
  • 当 DOFF 置为高电平时,DDR II 会有 1.5 个周期的读延迟
  • 如需更多信息,请参阅 PDF 文档。
     

功能描述

CY7C1518KV18 和 CY7C1520KV18 是采用 DDR II 架构的 1.8 V 同步管线型(pipelined) SRAM。DDR II 包含一个带有先进同步外围电路的 SRAM 内核和一个 1 位突发计数器。用于读和写的地址被锁止在输入 (K) 时钟的备选上升沿。

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.

翻译文档仅作参考之用。我们建议您在参与设计开发时参考文档的英语版本。