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CY7C1568KV18, CY7C1570KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | 赛普拉斯半导体

CY7C1568KV18, CY7C1570KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

最近更新: 
2016 年 3 月 15 日
版本: 
*R

72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

特性

  • 72 Mbit 密度 (4M x 18, 2M x 36)
  • 550 MHz 时钟实现高带宽
  • 2 字突发降低地址总线频率
  • 双数据速率 (DDR) 接口(数据传输速率 1100 MHz),工作频率 550 MHz
  • 可提供 2.5 时钟周期延迟
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
    • SRAM 仅使用上升沿
  • 回波时钟(CQ 和 CQ)简化高速系统中的数据采集
  • 数据有效引脚 (QVLD) 表示输出上的有效数据
  • 如需更多信息,请参阅 PDF 文档
     

功能描述

CY7C1568KV18 和 CY7C1570KV18 是采用 DDR II+ 架构的 1.8 V 同步管线型(pipelined)SRAM。DDR II+ 包含一个带有先进同步外围电路的 SRAM 内核。用于读和写的地址被锁止在输入 (K) 时钟的备选上升沿。

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.

翻译文档仅作参考之用。我们建议您在参与设计开发时参考文档的英语版本。