CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture | 赛普拉斯半导体
CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
- 144-Mbit density (8 M × 18)
- 333 MHz 时钟实现高带宽
- 2 字突发降低地址总线频率
- 双数据速率 (DDR) 接口（数据传输速率 666 MHz），工作频率 333 MHz
- 两个输入时钟（K 和 K）用于精确 DDR 定时
- SRAM 仅使用上升沿
- 两个输入时钟用于输出数据（C 和 C），以将时钟偏移和飞行时间的不匹配降至最低
- 回波时钟（CQ 和 CQ）简化高速系统中的数据采集
- 如需更多信息，请参阅 PDF 文档。
The CY7C1623KV18 is 1.8 V Synchronous Pipelined SRAM, equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. DDR-II SIO 包含两个分立的端口：即用于访问内存阵列的读端口和写端口。读端口具有数据输出来支持读操作，写端口则具有数据输入来支持写操作。The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus.
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
For the full version of this message, please download the PDF version.