CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) | 赛普拉斯半导体
CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
- 144-Mbit density (8 M × 18, 4 M × 36)
- 450-MHz clock for high bandwidth
- 2 字突发降低地址总线频率
- 双数据速率 (DDR) 接口（数据传输速率 900 MHz），工作频率 450 MHz
- Available in 2.0-clock cycle latency
- 两个输入时钟（K 和 K）用于精确 DDR 定时
- SRAM 仅使用上升沿
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- 数据有效引脚 (QVLD) 表示输出上的有效数据
- DDR II+ operates with 2.0-cycle read latency when DOFF is asserted high
The CY7C1648KV18, and CY7C1650KV18 are 1.8-V synchronous pipelined SRAMs equipped with DDR II+ architecture. DDR II+ 包含一个带有先进同步外围电路的 SRAM 内核。用于读和写的地址被锁止在输入 (K) 时钟的备选上升沿。Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two18-bit words (CY7C1648KV18), or 36-bit words (CY7C1650KV18) that burst sequentially into or out of the device.
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