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CY7C1663KV18/CY7C1665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) | 赛普拉斯半导体

CY7C1663KV18/CY7C1665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

最近更新: 
2018 年 1 月 29 日
版本: 
*O
The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture.

144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

特性

  • 分立的独立读和写数据端口
    • 支持并发事务处理
  • 550 MHz 时钟实现高带宽
  • 4 字突发降低地址总线频率
  • 读和写端口均为双倍数据速率 (DDR) 接口(数据传输速率 1100 MHz),工作频率 550 MHz
  • 可提供 2.5 时钟周期延迟
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
    • SRAM 仅使用上升沿
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • 数据有效引脚 (QVLD) 表示输出上的有效数据
  • Single multiplexed address input bus latches address inputs for read and write ports
  • 如需更多信息,请参阅 PDF 文档。

功能描述

The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. 与 QDR II 架构类似,QDR II+ 架构也包含两个分立的端口:即用于访问内存阵列的读端口和写端口。读端口有专用的数据输出来支持读操作,写端口则有专用的数据输入来支持写操作。QDR II+ 架构具有单独的数据输入和数据输出,完全消除了公用 I/O 器件上存在的“转换”数据总线方面的需要。Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

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Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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