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CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | 赛普拉斯半导体

CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

最近更新: 
2018 年 1 月 29 日
版本: 
*J

18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

特性

  • 18 Mbit density (1 M x 18, 512 K x 36)
  • 550 MHz 时钟实现高带宽
  • 2 字突发降低地址总线频率
  • 双数据速率 (DDR) 接口(数据传输速率 1100 MHz),工作频率 550 MHz
  • 可提供 2.5 时钟周期延迟
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
    • SRAM 仅使用上升沿
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • 数据有效引脚 (QVLD) 表示输出上的有效数据
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. DDR II+ 包含一个带有先进同步外围电路的 SRAM 内核。用于读和写的地址被锁止在输入 (K) 时钟的备选上升沿。

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