CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR(R) II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | 赛普拉斯半导体
CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR(R) II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
- 450 MHz 时钟实现高带宽
- 2 字突发降低地址总线频率
- 读和写端口均为双倍数据速率 (DDR) 接口（数据传输速率 900 MHz），工作频率 450 MHz
- 可提供 2.5 时钟周期延迟
- 两个输入时钟（K 和 K）用于精确 DDR 定时
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- 数据有效引脚 (QVLD) 表示输出上的有效数据
- On-Die Termination (ODT) feature
- 如需更多信息，请参阅 PDF 文档
The CY7C2262XV18, and CY7C2264XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. 与 QDR II 架构类似，QDR II+ 架构也包含两个分立的端口：即用于访问内存阵列的读端口和写端口。读端口有专用的数据输出来支持读操作，写端口则有专用的数据输入来支持写操作。QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common devices.
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
For the full version of this message, please download the PDF version.