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CY7C2568XV18, CY7C2570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | 赛普拉斯半导体

CY7C2568XV18, CY7C2570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

最近更新: 
2015 年 8 月 27 日
版本: 
*E

72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

特性

  • 72-Mbit density (4 M × 18, 2 M × 36)
  • 633 MHz 时钟实现高带宽
  • 2 字突发降低地址总线频率
  • 双数据速率 (DDR) 接口(数据传输速率 1266 MHz),工作频率 633 MHz
  • 可提供 2.5 时钟周期延迟
  • 两个输入时钟(K 和 K)用于精确 DDR 定时
  • 回波时钟(CQ 和 CQ)简化高速系统中的数据采集
  • 数据有效引脚 (QVLD) 表示输出上的有效数据
  • On-die termination (ODT) feature
  • 如需更多信息,请参阅 PDF 文档

功能描述

The CY7C2568XV18, and CY7C2570XV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. DDR II+ 包含一个带有先进同步外围电路的 SRAM 内核。用于读和写的地址被锁止在输入 (K) 时钟的备选上升沿。Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C2568XV18), or 36-bit words (CY7C2570XV18) that burst sequentially into or out of the device.