CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT | 赛普拉斯半导体
CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
- 333-MHz clock for high bandwidth
- 2 字突发降低地址总线频率
- 读和写端口均为双倍数据速率 (DDR) 接口（数据传输速率 666 MHz），工作频率 333 MHz
- Available in 2.0-clock cycle latency
- 两个输入时钟（K 和 K）用于精确 DDR 定时
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- 数据有效引脚 (QVLD) 表示输出上的有效数据
- On-die termination (ODT) feature
- 如需更多信息，请参阅 PDF 文档
The CY7C2642KV18, and CY7C2644KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II+ architecture. 与 QDR II 架构类似，QDR II+ 架构也包含两个分立的端口：即用于访问内存阵列的读端口和写端口。读端口有专用的数据输出来支持读操作，写端口则有专用的数据输入来支持写操作。QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.
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