CY7S1061G, CY7S1061GE: 16-Mbit (1 M words × 16 bit) Static RAM with Deep-Sleep Feature and Error-Correcting Code (ECC) | 赛普拉斯半导体
CY7S1061G, CY7S1061GE: 16-Mbit (1 M words × 16 bit) Static RAM with Deep-Sleep Feature and Error-Correcting Code (ECC)
16-Mbit (1 M words × 16 bit) Static RAM with Deep-Sleep Feature and Error-Correcting Code (ECC)
- High speed
- tAA = 10 ns
- Ultra-low power PowerSnooze™ device
- Deep Sleep (DS) current IDS = 22-µA maximum
- Low active and standby currents
- ICC = 90-mA typical
- ISB2 = 20-mA typical
- 宽广的工作电压范围：1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V
- Embedded error-correcting code (ECC) for single-bit error correction
- 1.0-V data retention
- Transistor-transistor logic (TTL) compatible inputs and outputs
- Error indication (ERR) pin to indicate 1-bit error detection and correction
- Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages
The CY7S1061G/CY7S1061GE is a high-performance CMOS fast static RAM organized as 1,048,576 words by 16 bits. This device features fast access times (10 ns) and a unique ultra-low power Deep Sleep mode. With Sleep mode currents as low as 22 μA, the CY7S1061G device combines the best features of fast and low-power SRAM in industry-standard package options. The device also features embedded ECC. ECC logic can detect and correct single-bit error in the accessed location. The CY7S1061GE device includes an ERR pin that signals an error-detection and correction event during a read cycle.
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