You are here

CYDXXS72V18, CYDXXS36V18, CYDXXS18V18: FullFlex™ Synchronous SDR Dual Port SRAM | 赛普拉斯半导体

CYDXXS72V18, CYDXXS36V18, CYDXXS18V18: FullFlex™ Synchronous SDR Dual Port SRAM

最近更新: 
2019 年 3 月 04 日
版本: 
**

FullFlex™ Synchronous SDR Dual Port SRAM

特性

  • True dual port memory enables simultaneous access to the shared array from each port
  • Synchronous pipelined operation with single data rate (SDR) operation on each port
    • SDR interface at 200 MHz
    • Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
  • Selectable pipelined or flow-through mode
  • 1.5 V or 1.8 V core power supply
  • Commercial and Industrial temperature
  • IEEE 1149.1 JTAG boundary scan
  • Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages
  • 如需更多信息,请参阅 PDF 文档

     

功能描述

The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

翻译文档仅作参考之用。我们建议您在参与设计开发时参考文档的英语版本。