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S25FS064S, 64 MBIT (8 MBYTE), 1.8 V FS-S FLASH | Cypress Semiconductor

S25FS064S, 64 MBIT (8 MBYTE), 1.8 V FS-S FLASH

最近更新: 
2019 年 4 月 28 日
版本: 
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The FS-S Family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.

The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms

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