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S70FL256P: 256-Mbit 3.0 V Flash Memory | 赛普拉斯半导体

S70FL256P: 256-Mbit 3.0 V Flash Memory

2016 年 3 月 22 日

This product is not recommended for new and current designs. For new and current designs, the S25FL256S supersedes S70FL256P. This is the factory-recommended migration path. Refer to the S25FL256S datasheet for specifications and ordering information, and AN98592 for changes required to migrate from existing designs based on S70FL256P.

Distinctive Characteristics

Architectural Advantages

Single power supply operation

  • Full voltage range: 2.7 to 3.6V read and write operations


  • Uniform 64 kB sectors
    • Top or bottom parameter block (Two 64-kB sectors broken down into sixteen 4-kB sub-sectors each) for each Flash die
  • Uniform 256 kB sectors (no 4-kB sub-sectors)
  • 256-byte page size


  • Page Program (up to 256 bytes) in 1.5 ms (typical)
  • Program operations are on a page by page basis
  • Accelerated programming mode via 9V W#/ACC pin
  • Quad Page Programming


  • Bulk erase function for each Flash die
  • Sector erase (SE) command (D8h) for 64 kB and 256 kB sectors
  • Sub-sector erase (P4E) command (20h) for 4 kB sectors (for uniform 64-kB sector device only)
  • Sub-sector erase (P8E) command (40h) for 8 kB sectors (for uniform 64-kB sector device only)


This document contains information for the S70FL256P device, which is a dual die stack of two S25FL129P die.