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PSoC® 5LP Architecture TRM | 赛普拉斯半导体

PSoC® 5LP Architecture TRM

最近更新: 
2019 年 11 月 17 日
版本: 
*G

This document encompasses the PSoC® 5LP family of devices. In conjunction with the device datasheet, it contains complete and detailed information about how to design with the IP blocks that construct a PSoC 5LP device. This document describes the analog and digital architecture, and helps to better understand the features of the device.

Programmable System-on-Chip (PSoC®) is a true system-level solution, offering a modern method of signal acquisition, processing, and control with exceptional accuracy, high bandwidth, and superior flexibility.