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用户模块数据表:8-Bit Delta Sigma ADC Datasheet DELSIG8 V 3.2 (CY8C29/27/24/22xxx, CY8C23x33, CY8CLED08/16, CY8C28x45) | Cypress Semiconductor

用户模块数据表:8-Bit Delta Sigma ADC Datasheet DELSIG8 V 3.2 (CY8C29/27/24/22xxx, CY8C23x33, CY8CLED08/16, CY8C28x45)

最近更新: 
2015 年 3 月 27 日
版本: 
3.2

功能和概述

  • 8 位分辨率
  • 适合于 2 的补码的数据格式
  • Sample rate up to 32 ksps
  • 64X over sampling with sinc2 filter reduces antialias requirements
  • 内部和外部参考选项所定义的输入范围
  • 内部或外部时钟
  • Second order modulator available for the CY8C29/27/24/22xxx, CY8C23x33, CY8CLED08/16,CY8C28x45 families of PSoC devices
     

注意:  如果此用户模块用于 29K 系列,它将额外消耗 6 毫安。替代方法是使用 Delsig 用户模块。

The DELSIG8 User Module provides an 8-bit 2’s complement conversion of an 2.6 volt full scale input signal centered around a user selected AGND, when the reference selection in the global parameter window is set to ± Bandgap. It supports sample rates from 1.8 ksps to 31 ksps. 采样率由数据时钟输入确定,但用户可以选择。Data generated by the DELSIG8 is available in the interrupt routine where the data is collected or through polling functions furnished by the DELSIG8 API.